1. Field of the Invention
The present invention relates to a material comprising a substrate, one of the surfaces of which is covered with a layer based on a block copolymer, and to its applications for:                manufacturing a material useful for electronics, notably manufacturing flash memories, vertical transistors, non-sequential access memory (RAM), transistors according to the FET and CMOS technologies,        for preparing organic light-emitting diodes (OLED) or components of organic photovoltaic cells (OPV), or        for designing detection devices (nanobiosensors, biochips) which may be used in chemistry, agrofood industry or in the field of health care.        
The self-assembling of block copolymers gives the possibility of controlling the organization of nanodomains, and thereby preparing films with an integration density of various nanometric objects (holes, studs, lamellas, pillars, layers . . . ) suitable for specific uses which require materials with a high density of active areas. This approach is of particular interest in industrial sectors, for which economic issues require exceeding the limits of conventional methods for developing increasingly miniaturized objects. For example, the development of microelectronics is limited by optical lithography or etching techniques. This is also the case of LED lighting which should exceed LCD, plasma technologies. Also, micro-array and micro-fluidic technologies are not suitable for the development of performing systems for simultaneous multi-detection and/or direct detection (SPR, SERS, fluorescent nanoprobes . . . ) of molecules or even at the scale of isolated molecules.
2. Description of the Related Art
U.S. Pat. No. 7,045,851 describes the use of a synthetic diblock copolymer consisting of polystyrene (PS) and of poly(methyl (meth)acrylate) (PMMA), deposited on a silicon oxide layer in order to form a discrete floating gate of a field effect transistor. The organized nanodomains based on PMMA blocks have a network period of the order of 40 nm.
Patent application EP 2 088 618 describes the use of a polystyrene (PS)-poly(methyl (meth)acrylate) (PMMA) diblock copolymer for preparing a lithographic mask. The method gives the possibility of preparing floating gates for microelectronics, for which the active area dimensions are 0.25×0.32 pm2.
Zhang et al. (Advanced Material 2007 19, 1571-1576) describes the use of a polystyrene (PS)-polyethyleneoxide (PEO) diblock copolymer for preparing a useful lithographic mask for microelectronics. Organized nanodomains based on PEO blocks have a network period of the order of 22 nm. The roadmap of the ITRS (International Technology Roadmap for Semiconductors, 2005 Edition) indicates that a network of nanodomains with a period of less than 22 nm is the <<technological node>>, to be exceeded before 2020 in order to meet the economic challenges of the microelectronics sector.